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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
March 2001 Ver. 0.8
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate ( board or glass) or product design stage. Always test and inspect products under the environment with no penetration of light.
2.
S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094 Specification Revision History Version 0.0 Original CGROM font table added at table 5 COM data shift direction changed at table 9 0.1 Read data instruction separation according to RE bit at table 10 Symbol register is changed to ICONRAM at table 12 IDD1 is changed at table 18, 19 0.2 0.3 0.4 IDD1 is changed at table 18, 19 Pad location added at table 1 and 2 VDD change (2.4V~5.5V -> 2.4V~3.6V) Inspection 0.5 0.6 0.7 0.8 ICON function addition (p21) IDD1 95 -> IDD1 80~110 (p53) Added detail information for several items Ta=-30E to 85E a Ta=-40E to 85E Jun.1999 July.1999 Nov.1999 Jun.2000 Sep.2000 Oct.2000 Mar.2001 May. 2002 May.1999 Content Date Apr.1999
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
CONTENTS
INTRODUCTION .....................................................................................................................................1 FEATURES .............................................................................................................................................1 BLOCK DIAGRAM ..................................................................................................................................3 PAD CONFIGURATION ..........................................................................................................................4 PAD CENTER COORDINATES ..............................................................................................................5 PIN DESCRIPTION .................................................................................................................................5 POWER SUPPLY .............................................................................................................................6 LCD DRIVER SUPPLY .....................................................................................................................6 SYSTEM CONTROL.........................................................................................................................7 MPU INTERFACE ............................................................................................................................8 LCD DRIVER OUTPUTS ...................................................................................................................8 TEST ...............................................................................................................................................8 FUNCTION DESCRIPTION......................................................................................................................9 SYSTEM INTERFACE ......................................................................................................................9 ADDRESS COUNTER (AC) ............................................................................................................ 13 DISPLAY DATA RAM (DDRAM) ...................................................................................................... 13 CHARACTER GENERATOR ROM (CGROM) .................................................................................. 13 CHARACTER GENERATOR RAM (CGRAM)................................................................................... 19 SEGMENT ICON RAM (ICONRAM)................................................................................................. 20 HIGH POWER MODE ..................................................................................................................... 22 LOW POWER CONSUMPTION MODE ............................................................................................ 22 LCD DRIVER CIRCUIT ................................................................................................................... 23 INSTRUCTION DESCRIPTION .............................................................................................................. 24 INITIALIZING & POWER SAVE MODE SETUP ...................................................................................... 35 HARDWARE RESET...................................................................................................................... 35 INITIALIZING AND POWER SAVE SETUP ...................................................................................... 37 LCD DRIVING POWER SUPPLY CIRCUIT............................................................................................. 40 VOLTAGE CONVERTER ................................................................................................................ 40 VOLTAGE REGULATOR ................................................................................................................ 41 ELECTRONIC CONTRAST CONTROL (32 STEPS)......................................................................... 42 VOLTAGE GENERATOR CIRCUIT ................................................................................................. 44 MPU INTERFACE ................................................................................................................................. 45 APPLICATION INFORMATION FOR LCD PANEL .................................................................................. 47 FRAME FREQUENCY........................................................................................................................... 51 MAXIMUM ABSOLUTE RATINGS ......................................................................................................... 52 ELECTRICAL CHARACTERISTICS ....................................................................................................... 53 DC CHARACTERISTICS ................................................................................................................ 53 AC CHARACTERISTICS ................................................................................................................. 54
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
INTRODUCTION
The S6A0094 is an LCD driver and controller LSI for liquid crystal dot matrix character display systems. It can display 2, 3 or 4 lines of 16 characters with 5 x 8 dots format. It is capable of interfacing various microprocessors, supporting the 4 -bit, 8-bit parallel modes and the clock synchronized serial mode. Voltage converter, oscillator, voltage regulator, voltage follower and bias circuit are built in the IC. The double height character mode and line vertical scroll functions are supported.
FEATURES
Driver Outputs Common outputs: 34 common Segment outputs: 80 segment
Applicable Panel Size Font Display 2-line x 16 characters 1 / 18 5x8 3-line x 16 characters 4-line x 16 characters Internal Memory Character Generator ROM (CGROM): 21,760 bits (544 characters x 5 x 8 dots) Character Generator RAM (CGRAM): 240 bits (6 characters x 5 x 8 dots) Display Data RAM (DDRAM): 640 bits (16 characters x 5 lines ) Segment Icon RAM (ICONRAM): 160 bits (160 icons) 1 / 26 1 / 34 3 x 16 characters + 160 icons 4 x 16 characters + 160 icons 2 x 16 characters + 160 icons Duty Contents of outputs
MPU Interface No busy MPU interface (no busy check or no execution waiting time) 8-bit parallel interface mode: 68-series and 80-series are available 4-bit parallel interface mode: 68-series and 80-series are available Serial interface mode: 4-pin clock synchronized serial interface
Function Set Various instructions set: display control, power save, power control, etc. COM / SEG bi-directional ( 4-type LCD application available) H/W reset (RESETB)
Built-in Analog Circuit Internal RC oscillator circuit or external clock Electronic volume for contrast control (32 steps) Voltage converter / voltage regulator / voltage follower & bias circuit
Low Power Operation Sleep mode operation (5uA Max.) Normal mode operation (TBD)
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
Operating Voltage Range Power supply voltage (VDD): 2.2V - 3.6V LCD driving voltage (VLCD = V0 - VSS): 7.0V Max.
Package Type Gold bumped chip
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
BLOCK DIAGRAM
RESETB PS IF MI CSB RS RW_WR E_RD DB7 (SI) DB6 (SCL) DB5DB4 DB3DB0 8 DUTY1 DUTY0 Character Generator RAM (CGRAM) 240 bits 5 VDD GND Segment Data Conversion Serial Interface Input Buffer 8 Instruction Register (IR) Oscillator Timing Generator CK
Parallel Interface 4 bit/8 bit
8
Instruction Decoder Display Data RAM (DDRAM) 640 bits 7 8 8 80 bits Shift Register 80 bits Latch Circuit 34 bits Shift Register
COM1Common COM32 Driver COM I1 COM I2
Address Counter Data Register (DR) Data Output Register (OR)
8
SEG1Segment SEG80 Driver
88 Character Generator ROM (CGROM) 21760 bits 5
Icon RAM 160 bits
Cursor and Blink Controller
LCD Driver Voltage Selector
LCD Driving Power Circuit Voltage Converter Voltage Regulator Voltage Follower & Bias Resistor
CAP1+ CAP1- CAP2+ CAP2-
VOUT
V0 VR
V1 V2 V3 V4
DIRS
Figure 1. Block Diagram
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
PAD CONFIGURATION
163
............................
82
164
.. ...
Y X
81
...
(0,0) 183 1
...........................
62 61
DUMMY PAD PAD
Figure 2. Pad Configuration Table 1. S6A0094 Pad Dimensions Item Chip size Pad No. 1 - 66 Pad pitch 63~80,83~162,165~182 62,81,82,163,164,183 1~61 63~80 83~162 Bumped pad size 165~182 62,81 82,163 164,183 Bumped pad height COG Align Key Coordinate
30 m 30m 30 m 30m 30m 30 m 30m 30 m 30 m 30 m
Size X 6320 90 70 90 60 100 50 100 100 60 100 17 (Typ.) 100 50 100 50 60 100 60 Y 1860
Unit
m
m
All pad
m
ILB Align Key Coordinate(with Gold Bump)
42m 108m 42m 108m
(-3110, +880)
(+3110, +880)
42m
42m
(-2830, -835)
* When designing electrode pattern must be prohibited on this area (ILB Align Key). If electrode pattern is used for routing over this area, it can be happened pattern-short through gold bump pattern on ILB Align Key.
60m
(+2830, -830)
108m
108m
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates [Unit: m]
Pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
Pad Name RS VSS RW_WR VDD E_RD VSS CSB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VDD VDD VSS VSS V4 V4 V3 V3 V2 V2 V1 V1 V0 V0 V0 V0 VR VR VSS DUTY1 VDD DUTY0 VSS VOUT VOUT CAP2CAP2CAP2+ CAP2+ CAP1CAP1CAP1+ CAP1+ VSS DIRS VDD CK VSS PS VDD IF VSS MI VDD RESETB TEST
X -2700 -2610 -2520 -2430 -2340 -2250 -2160 -2070 -1980 -1890 -1800 -1710 -1620 -1530 -1440 -1350 -1260 -1170 -1080 -990 -900 -810 -720 -630 -540 -450 -360 -270 -180 -90 0 90 180 270 360 450 540 630 720 810 900 990 1080 1170 1260 1350 1440 1530 1620 1710 1800 1890 1980 2070 2160 2250 2340 2430 2520 2610 2700
Y -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820
Pad No 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122
Pad Name DUMMY1 COMI1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COMI1 DUMMY2 DUMMY3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40
X 3050 3050 3050 3050 3050 3050 3050 3050 3050 3050 3050 3050 3050 3050 3050 3050 3050 3050 3050 3050 2845 2765 2695 2625 2555 2485 2415 2345 2275 2205 2135 2065 1995 1925 1855 1785 1715 1645 1575 1505 1435 1365 1295 1225 1155 1085 1015 945 875 805 735 665 595 525 455 385 315 245 175 105 35
Y -700 -620 -550 -480 -410 -340 -270 -200 -130 -60 10 80 150 220 290 360 430 500 570 650 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820
Pad No 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183
Pad Name SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 DUMMY4 DUMMY5 COMI2 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COMI2 DUMMY6
X -35 -105 -175 -245 -315 -385 -455 -525 -595 -665 -735 -805 -875 -945 -1015 -1085 -1155 -1225 -1295 -1365 -1435 -1505 -1575 -1645 -1715 -1785 -1855 -1925 -1995 -2065 -2135 -2205 -2275 -2345 -2415 -2485 -2555 -2625 -2695 -2765 -2845 -3050 -3050 -3050 -3050 -3050 -3050 -3050 -3050 -3050 -3050 -3050 -3050 -3050 -3050 -3050 -3050 -3050 -3050 -3050 -3050
Y 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 820 650 570 500 430 360 290 220 150 80 10 -60 -130 -200 -270 -340 -410 -480 -550 -620 -700
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
PIN DESCRIPTION
POWER SUPPLY
Table 3. Pin Description Name VDD VSS I/O Power supply Power Connect to MPU power supply pin 0V (GND) Bias voltage level for LCD driving Voltages should have the following relationship; V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 I/O When the built-in power circuit is active and internal 1/5 bias resistors are used. LCD bias V1 V2 V3 V4 Description
1/5 bias (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0 When the built-in power circuit is active and internal 1/4 bias resistors are used. LCD bias 1/4 bias V1 (3/4) x V0 V2 V3 V4 (1/4) x V0
(2/4) x V0
LCD DRIVER SUPPLY
Table 3. Pin Description (Continued) Name CAP1+ CAP1CAP2+ CAP2VOUT VR I/O O O O O I/O I Description Capacitor + connecting pin for the internal voltage converter Capacitor - connecting pin for the internal voltage converter Capacitor + connecting pin for the internal voltage converter Capacitor - connecting pin for the internal voltage converter DC/DC voltage converter output Voltage adjust pin This pin gives a voltage between V0 and VSS by resistance-division of voltage.
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
SYSTEM CONTROL
Table 3. Pin Description (Continued) Name I/O Description External clock input It must be fixed to "High" or "Low" when the internal oscillation circuit is used. In case of the external clock mode, CK is used as the clock and OS bit should be OFF. MPU interface selection input MI = "Low": 80 series MPU MI = "High": 68 series MPU Parallel / Serial selection input When PS = "Low": Serial mode When PS = "High": 4-bit/8-bit bus mode Interface data length selection pin for parallel data input When PS = "Low" IF = "Low" or "High": serial interface mode When PS = "High" IF = "Low": 4-bit bus mode IF = "High": 8-bit bus mode SEG direction selection input When DIRS = "Low" SEG1 SEG2 SEG79 SEG80 When DIRS = "High" SEG80 SEG79 SEG2 SEG1 Display line mode selection input DUTY1 DUTY1 DUTY0 I 0 0 1 DUTY0 0 1 0/1 Mode 2-line 3-line 4-line Duty 1/18 1/26 1/34
CK
I
MI
I
PS
I
IF
I
DIRS
I
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
MPU INTERFACE
Table 3. Pin Description (Continued) Name RESETB CSB I/O I I Description Reset input S6A0094 is initialized while RESETB is low. Chip selection input S6A0094 is selected while CSB is low. Register selection input When RS = "Low", instruction register When RS = "High", data register In 80-series MPU interface mode This pin is connected to WR pin of MPU and is an active low write signal. In 68-series MPU interface mode This pin is connected to R/W pin of MPU. When RW_WR = "Low", write mode When RW_WR = "High", read mode In 80-series MPU interface mode This pin is connected to RD pin of MPU and is a active low read signal. In 68-series MPU interface mode This pin is connected to E pin of MPU and enable read or write command according to RW_WR signal. When 8-bit bus mode, used as bi-directional data bus DB0 - DB7. During 4-bit bus mode, only DB4 - DB7 are used. In this case DB0 - DB3 pins are not used. When serial mode, DB6 (SCL) is used as serial clock input pin and DB7 (SI) is used as serial data input pin.
RS
I
RW_WR
I
E_RD
I
DB0 - DB3 DB4 - DB5 DB6 (SCL), DB7 (SI) I/O
LCD DRIVER OUTPUTS
Name COM1 - COM32 COMI1, COMI2 SEG1 - SEG80 I/O O O O Description Common signal output for driving LCD Common signal output for icon display Segment signal output for driving LCD
TEST
Name TEST I/O I Description Test pin This pin is not used for normal operation. Open at normal operation mode
NOTE: DUMMY - These pins should be opened (floated).
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
FUNCTION DESCRIPTION
SYSTEM INTERFACE
S6A0094 has two kinds of interface type with MPU: bus mode, serial mode. Serial or bus mode is selected by PS pin. In bus mode, 4-bit bus or 8-bit bus is selected by IF pin, and 68 series MPU or 80 series MPU is selected by MI pin. Table 4. Various Kinds of MPU Interface according to PS, MI and IF
PS MI 68 series Bus mode (H) (H) 80 series (L) Serial mode (L) (H)/(L)(2) IF 8 bit (H) 4 bit (L) 8 bit (H) 4 bit (L) (H)/(L) CSB CSB CSB CSB CSB CSB RS RS RS RS RS RS RW_WR R/W R/W WR WR (H)/(L) E_RD E E RD RD (H)/(L) DB0 DB3 DB0DB3
(1)
DB4 DB5 DB4DB5 DB4DB5 DB4DB5 DB4DB5
DB6 DB6 DB6 DB6 DB6 SCL
DB7 DB7 DB7 DB7 DB7 SI
DB0DB3
NOTES: 1. ` * `: Don't care (High, Low or Open) 2. ` (H)/(L) `: Fixed High (VDD) or Low (VSS)
PS: "High" = bus mode, "Low" = serial mode MI: "High" = 68-series MPU, "Low" = 80-series MPU IF: "High" = 8-bit mode, "Low" = 4-bit mode (PS: "High") CSB: "High" = chip is not selected, "Low" = chip is selected RS: "High" = data register, "Low" = instruction register RW_WR : read / write indicating signal in 68 mode or active low signal for enabling write in 80 mode. E_RD: active high signal for enabling command is 68 mode or active low signal for enabling read in 80 mode. SCL (DB6): serial clock input SI (DB7): serial data input
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
Interface with MPU in Parallel Mode (PS = "High") During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. The data register (DR) is used as temporary data storage place for being written into DDRAM / CGRAM / ICONRAM and one of these RAM is selected by R AM address setting instruction. The Instruction register (IR) is used only to store instruction code transferred from MPU. To select DR or IR register, RS input pin is used. During reading operation, 8-bit register, output data register (OR) is used. The output data register (OR) is used as temporary data storage place for being read from DDRAM / CGRAM / ICONRAM and one of these RAM is selected by RAM address setting instruction. After RAM address setting, first reading is a dummy cycle in 8-bit bus mode (figure 3, 4). The valid data comes from second reading. In 4 -bit bus mode, after RAM address setting, first and second reading are dummy cycles (figure 5, 6). The valid data comes from third reading. The dummy read make the address counter (AC) increased by 1. So it is recommended to set address again before writing. The instruction read cycle is not supported and it is regarded as a no operation cycle. In 4-bit bus mode, it is needed to transfer 4-bit data (through DB7-DB4) by two times. The high order bits (for 8-bit mode DB7-DB4) are written before the low order bits (for 8-bit mode DB3-DB0) in write and low order bits (for 8-bit mode DB3-DB0) are read before the high order bits (for 8-bit mode DB7-DB4) in read transaction. The DB0-DB3 pins are floated in this 4-bit bus mode. After RESETB resets, S6A0094 considers first 4-bit data from MPU as the high order bits.
IF MI CSB RS RW_WR E_RD DB7-DB0
Instruction Write NOP Dummy Read
Valid Data
RAM Read
Data Write
Figure 3. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
IF MI CSB RS RW_WR E_RD DB7-DB0
Instruction Write NOP Dummy Read
Valid Data
RAM Read
Data Write
Figure 4. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)
IF MI CSB RS RW_WR E_RD DB7-DB4
upper 4-bit lower 4-bit upper 4-bit lower 4-bit upper 4-bit lower 4-bit
Instruction Write
NOP
Dummy Read
RAM Read
Data Write
Figure 5. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)
IF MI CSB RS RW_WR E_RD DB7-DB4
upper 4-bit lower 4-bit upper 4-bit lower 4-bit upper 4-bit lower 4-bit
Instruction Write
NOP
Dummy Read
RAM Read
Data Write
Figure 6. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
Interface with MPU in Serial Mode (PS = "Low") When PS input pin is "Low", clock synchronized serial interface mode is selected. At this time, four ports, SCL (DB6, synchronizing transfer clock), SI (DB7, serial input data), RS (register selection input) and CSB (chip selection input) are used. By setting CSB to "Low", S6A0094 can receive SCL input. If CSB is set to "High", S6A0094 resets the internal 8-bit shift register and 3-bit counter. Serial data is input in the order of "D7, D6, D5, D4, D3, D2, D1, D0" from the serial data input pin (SI = DB7) at the rising edge of serial clock (SCL = DB6). At the rising edge of the 8th serial clock, the serial data (D7-D0) is converted into 8 bit bus mode data. The RS input of the DR/IR selection is latched at the rising edge of the 8th serial clock (SCL). In serial mode, the read is not possible.
CSB S I (DB7) SCL (DB6) RS
1
D7
2
D6
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
9
D7
Figure 7. Timing Diagram of Serial Data Transfer
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
ADDRESS COUNTER (AC)
Address Counter (AC) in S6A0094 stores DDRAM / CGRAM / ICONRAM address. After writing into or reading from DDRAM / CGRAM / ICONRAM, AC is automatically increased by 1. The address counter is only one and stores the address among DDRAM / CGRAM / ICONRAM.
DISPLAY DATA RAM (DDRAM)
DDRAM stores display data of maximum 80 x 8 bits (Max. 80 characters). DDRAM address is set in the address counter (AC) as a hexadecimal number.
1st Ch.
16th Ch.
COM1 COM9
COM8 COM16
30 40 50 60 70
31 41 51 61 71
32 42 52 62 72
33 43 53 63 73
34 44 54 64 74
35 45 55 65 75
36 46 56 66 76
37 47 57 67 77
38 48 58 68 78
39 49 59 69 79
3A 4A 5A 6A 7A
3B 4B 5B 6B 7B
3C 4C 5C 6C 7C
3D 4D 5D 6D 7D
3E 4E 5E 6E 7E
3F 4F 5F 6F 7F
COM17 COM24 COM25 COM32 Hidden Line
SEG1
SEG80
DDRAM Address in 4 line Display
Figure 8. DDRAM Address
CHARACTER GENERATOR ROM (CGROM)
CGROM has one main ROM and four option ROM. The main CGROM has 160 characters and the option CGROMs have 96 characters each. The total CGROM has 5 x 8-dot 544 characters. The R1, R0 bits select an option CGROM between 4 option CGROM. If one of 4 CGROM is selected, the other CGROM font can not be used. The CG bit of the instruction table selects the 6 characters (00h 05h) of CGROM or CGRAM.
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
Table 5. CGROM Character Code (Main ROM)
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S6A0094
Table 5. CGROM Character Code (Option ROM1) (Continued)
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
Table 5. CGROM Character Code (Option ROM2) (Continued)
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S6A0094
Table 5. CGROM Character Code (Option ROM3) (Continued)
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
Table 5. CGROM Character Code (Option ROM4) (Continued)
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S6A0094
CHARACTER GENERATOR RAM (CGRAM)
CGRAM has up to 5 x 8-dot 6 characters. By writing font data to C GRAM, user defined character can be used. CGRAM can be written regardless of CG bit. Table 6. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)
Character code (DDRAM data) D7 D6 D5 D4 D3 D2 D1 D0 RE CGRAM address A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CGRAM data P7 P6 P5 P4 P3 P2 P1 P0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 Pattern number
00000000 (00h)
1
Pattern 1
00000001 (01h)
1
Pattern 2
00000010 (02h)
1
Pattern 3
00000011 (03h)
1
Pattern 4
NOTE: "-" - Don't care
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
Table 6. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM) (continued)
Character code (DDRAM data) D7 D6 D5 D4 D3 D2 D1 D0 RE CGRAM address A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CGRAM data P7 P6 P5 P4 P3 P2 P1 P0 1 1 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 0 0 1 1 0 0 Pattern number
00000100 (04h)
1
Pattern 5
00000101 (05h)
1
Pattern 6
NOTE: "-" - Don't care
SEGMENT ICON RAM (ICONRAM)
ICONRAM has segment control data and segment pattern data. The number of icons is 160.
S1 ... ...
S5
S76 ... ...
S80
COMI1
COMI2
......
S81
......
S85
S156
S160
Figure 9. Relationship between ICONRAM and Icon Display
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
Table 7. Relationship between ICONRAM Address and Display Pattern RE 1 1 . . 1 1 1 1 . . 1 1
NOTE1: "-" - Don't care
ICONRAM address D7 60h 61h . . 6Eh 6Fh 70h 71h . . 7Eh 7Fh BONF BONF ... BONF BONF BONF BONF ... BONF BONF D6 IORHIORH ... IORH IORH IORH IORH ... IORH IORH D5 ... ... -
ICONRAM bits D4 S1 S6 ... S71 S76 S81 S86 ... S151 S156 D3 S2 S7 ... S72 S77 S82 S87 ... S152 S157 D2 S3 S8 ... S73 S78 S83 S88 ... S153 S158 D1 S4 S9 ... S74 S79 S84 S89 ... S154 S159 D0 S5 S10 ... S75 S80 S85 S90 ... S155 S160
D7(BONF) 0 1 1
D6(IORH) 0 1 No blink.
Function D4 to D0 blink in black-and-white reverse form. The bits of "1" out of D4 to D0 blink.
NOTE2: "-" - Don't care
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
HIGH POWER MODE
The power circuit built-in the S6A0094 is a low power consumption type (when the High Power mode is OFF). Accordingly, in the case of a large load liquid crystal or panel, the display quality may be degraded. In the case, the display quality can be improved by entering HPM = "1" by command. Before determining whether or not to use this mode. It is recommended to make a display check with real machine. In the case, the display quality cannot be improved satisfactorily though the power mode is set, a liquid crystal driver power must be supplied from the outside.
LOW POWER CONSUMPTION MODE
S6A0094 provides with sleep mode for saving power consumption during standby period. Sleep Mode (Power Save Bit ON, Oscillation Bit OFF) To enter the Sleep mode, the power circuit and oscillation circuit should be turned off by using the power save command and the power control command. This mode helps to save power consumption by reducing current to reset level. 1. Liquid Crystal Display Output COM1 - COM32, COMI1, COMI2 : VSS level SEG1 - SEG80 : VSS level 2. Data written in DDRAM, CGRAM, ICONRAM and registers are remained as previous value. 3. Operation mode is retained the same as it was prior to execution of the sleep mode. All internal circuits are stopped. 4. Power Circuit and Oscillation Circuit The built-in power supply circuit and oscillation circuit are turned off by power save command and power control command.
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
LCD DRIVER CIRCUIT
LCD Driver circuit has 34 commons and 80 segments signals for driving LCD. Data from ICONRAM / CGRAM / CGROM are transferred to 80-bit segment register serially, and then they are stored to 80-bit shift latch. In case of 2-line display mode COM1 - COM16, COMI1 and COMI2 have 1/18 duty, in 3-line mode COM1 - COM24, COMI1 and COMI2 have 1/26 duty, and in 4-line mode COM1 - COM32, COMI1 and COMI2 have 1/34 duty ratio. SEG bi-directional function is selected by DIRS input pin, and COM shift direction is selected by function set instruction "SS" bit. Table 8. SEG Data Shift Direction DIRS pin Low High SEG1 SEG2 SEG3 SEG80 SEG79 SEG78 SEG data shift direction ................... SEG78 SEG79 SEG80 SEG3 SEG2 SEG1
...................
Table 9. COM Data Shift Direction Line mode 2-line mode 3-line mode 4-line mode CS 0 (left) 1 (right) 0 (left) 1 (right) 0 (left) 1 (right) COM data shift direction COM1 COM2 .......... COM15 COM16 COMI1 COMI2 COM16 COM15 ........... COM2 COM1 COMI1 COMI2 COM1 COM2 ............ COM23 COM24 COMI1 COMI2 COM24 COM23 .............. COM2 COM1 COMI1 COMI2 COM1 COM2 ........... COM31 COM32 COMI1 COMI2 COM32 COM31 ............ COM2 COM1 COMI1 COMI2
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
INSTRUCTION DESCRIPTION
Table 10. Instruction Table
Instruction RE
0
RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 * * * *
Description
DDRAM address is set to 30h from AC and the cursor returns to home position The contents of DDRAM are not changed. Determination of the DDRAM line which is displayed at the first line at LCD LS1, LS0 = 00: DDRAM line 1 shows at the first line of LCD
Return home line shift 1 0 0 0 0 1 * * LS1 LS0
(default) 01: DDRAM line 2 shows at the first line of LCD 10: DDRAM line 3 shows at the first line of LCD 11: DDRAM line 4 shows at the first line of LCD
0
0
0
0
1
0
Line blink double height
Line blink mode LB4 = 0: DDRAM4 is normal display 1: DDRAM4 is blink mode LB3 = 0: DDRAM3 is normal display LB4 LB3 LB2 LB1 1: DDRAM3 is blink mode LB2 = 0: DDRAM2 is normal display 1: DDRAM2 is blink mode LB1 = 0: DDRAM1 is normal display 1: DDRAM1 is blink mode Doubled height mode DH4 = 0: DDRAM4 is normal display 1: DDRAM4 is double height DH3 = 0: DDRAM3 is normal display DH4 DH3 DH2 DH1 1: DDRAM3 is double height DH2 = 0: DDRAM2 is normal display 1: DDRAM2 is double height DH1 = 0: DDRAM1 is normal display 1: DDRAM1 is double height Cursor / blink / display ON / OFF
(default) (default) (default) (default)
(default) (default) (default) (default)
1
0
0
0
1
0
Display control 0/1
0
0
0
1
1
C
B
RE
D
C = 0: cursor OFF (default) 1: cursor ON B = 0: blink OFF (default) 1: blink ON RE=0: extension register OFF (default) 1: extension register ON D = 0: display OFF (default) 1: display ON
Power save
0/1
0
0
1
0
0
*
*
OS
Power save / oscillation circuit ON / OFF OS = 0: oscillator OFF (default) PS 1: oscillator ON PS = 0: power save OFF (default) 1: power save ON
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
Table 10. Instruction Table (Continued)
Instruction RE RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LCD power control HPM = 0: high power mode OFF (default) 1: High power mode ON VR = 0 : Voltage regulator OFF (default) VC 1 : Voltage regulator ON VF = 0 : Voltage follower OFF (default) 1 : Voltage follower ON VC = 0 : Voltage converter OFF (default) 1 : Voltage converter ON Internal resistor select IRS = 0: external resistors are used for regulator (default) 1: internal resistors are used for regulator LCD bias select BS = 0: 1/5 bias (default) IR0 1: 1/4 bias Internal resistor ratio select IR1, IR0 = 00: (1+Rb/Ra) = 2.81 01: (1+Rb/Ra) = 3.27 10: (1+Rb/Ra) = 3.50 11: (1+Rb/Ra) = 3.00 Option CGROM select R1,R0 = 00: main ROM + option ROM1 (default) 01: main ROM + option ROM2 10: main ROM + option ROM3 11: main ROM + option ROM4 CG Shifting direction of COM CS = 0: COM1 COM32 (default) 1: COM32 COM1 Select CGRAM or CGROM CG = 0: CGROM (default), 1: CGRAM Segment symmetry of each segment character 1 0 0 1 1 0 * * SS * SS = 0: normal character display (default) 1: symmetrical character display DDRAM or Electronic volume Address Range: 30h - 7Fh CGRAM or segment ICON RAM Address Range: 00h - 2Fh
Description
0
0
0
1
0
1
HPM VR
VF
Power control
1
0
0
1
0
1
IRS
BS
IR1
0 System set
0
0
1
1
0
R1
R0
CS
DDRAM / CGRAM address set
0
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
1
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write data
0/1
1
D7
D6
D5
D4
D3
D2
D1
Write DDRAM / CGRAM / ICONRAM /electronic volume RAM D0 This is determined by the address set instruction executed immediately before writing data. Read DDRAM / CGRAM / ICONRAM D0 This is determined by the address set instruction executed immediately before reading data. 0 * Non-operation Instruction Don't use this Instruction
Read data
0/1
1
D7
D6
D5
D4
D3
D2
D1
NOP Test
0/1 0/1
0 0
0 0
0 0
0 0
0 0
0 *
0 *
0 *
NOTES: 1. "-": Don't care 2. "*": Don't use
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
Return Home RE 0 RS 1 DB7 0 DB6 0 DB5 0 DB4 1 DB3 DB2 DB1 DB0 "-" : Don't care
Return Home instruction field makes cursor return home. DDRAM address is set to 30h from address counter and the cursor returns to home position. The contents of DDRAM are not changed. Line Shift Mode RE 1 RS 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 DB2 DB1 LS2 DB0 LS1
"-" : Don't care
Line Shift mode instruction field selects the DDRAM to be displayed in first line. LS1, LS0 = 00: scroll amount 0 line (default) 01: scroll 1 line upward (display line 1 from DDRAM line 2) 10: scroll 2 line upward (display line 2 from DDRAM line 3) 11: scroll 2 line upward (display line 3 from DDRAM line 4)
LCD
LCD
LCD
LCD
D D R A M L i n e 1 ( 3 0 h ~3 Fh) D D R A M L i n e 2 ( 4 0 h ~4 Fh) D D R A M L i n e 3 ( 5 0 h ~5 Fh) D D R A M L i n e 4 ( 6 0 h ~6 Fh) D D R A M L i n e 5 (7 0 h ~7 Fh)
LS2, LS1 = 00
D D R A M L i n e 2 ( 4 0 h ~4 Fh) D D R A M L i n e 3 ( 5 0 h ~5 Fh) D D R A M L i n e 4 ( 6 0 h ~6 Fh) D D R A M L i n e 5 (7 0 h ~7 Fh) D D R A M L i n e 1 ( 3 0 h ~3 Fh)
LS2, LS1 = 01
D D R A M L i n e 3 ( 50 h ~ 5Fh) D D R A M L i n e 4 ( 60 h ~ 6Fh) D D R A M L i n e 5 ( 70 h ~ 7Fh) D D R A M L i n e 1 ( 30 h ~ 3Fh) D D R A M L i n e 2 ( 40 h ~ 4Fh)
LS2, LS1 = 10
D D R A M L i n e 4 ( 6 0 h ~6 Fh) D D R A M L i n e 5 ( 7 0 h ~7 Fh) D D R A M L i n e 1 (3 0 h ~3 Fh) D D R A M L i n e 2 ( 4 0 h ~4 Fh) D D R A M L i n e 3 ( 5 0 h ~5 Fh)
LS2, LS1 = 11
Figure 10. Line Shift Mode Display at 3-line LCD
LCD
LCD
LCD
LCD
D D R A M L i n e 1 ( 3 0 h ~ 3Fh) D D R A M L i n e 2 ( 40 h ~ 4Fh) D D R A M L i n e 3 (5 0 h ~ 5 F h ) D D R A M L i n e 4 (6 0 h ~ 6 F h ) D D R A M L i n e 5 (70 h ~ 7Fh)
LS2, LS1 = 00
D D R A M L i n e 2 (40 h ~ 4Fh) D D R A M L i n e 3 (50 h ~ 5Fh) D D R A M L i n e 4 (60 h ~ 6Fh) D D R A M L i n e 5 (70 h ~ 7Fh) D D R A M L i n e 1 (30 h ~ 3Fh)
LS2, LS1 = 01
D D R A M L i n e 3 ( 50 h ~5 Fh) D D R A M L i n e 4 ( 60 h ~6 Fh) D D R A M L i n e 5 ( 70 h ~7 Fh) D D R A M L i n e 1 ( 30 h ~3 Fh) D D R A M L i n e 2 ( 40 h ~4 Fh)
LS2, LS1 = 10
D D R A M L i n e 4 (60 h ~ 6Fh) D D R A M L i n e 5 (70 h ~ 7Fh) D D R A M L i n e 1 (30 h ~ 3Fh) D D R A M L i n e 2 (40 h ~ 4Fh) D D R A M L i n e 3 (50 h ~ 5Fh)
LS2, LS1 = 11
Figure 11. Line Shift Mode Display at 4-line LCD
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
Line Blink Display Control RE 0 RS 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 LB4 DB2 LB3 DB1 LB2 DB0 LB1
Displays the specified line in black-and-white form. The specified line corresponds to the address line of DDRAM. Display the specified line of the DDRAM in black-and-white form by setting LB4 to LB1. Blinking is performed at the same frequency as cursor blink. If blinking is caused to occur at the same time, the cursor position will be hard to know. LB4 = 0: displays the data for line 4 of the DDRAM in standard form (no blink) (DDRAM 60H to 6FH) = 1: displays the data for line 4 of the DDRAM in black-and-white reverse blink form (DDRAM 60H to 6FH) LB3 = 0: displays the data for line 3 of the DDRAM in standard form (no blink) (DDRAM 50H to 5FH) = 1: displays the data for line 3 of the DDRAM in black-and-white reverse blink form (DDRAM 50H to 5FH) LB2 = 0: displays the data for line 2 of the DDRAM in standard form (no blink) (DDRAM 40H to 4FH) = 1: displays the data for line 2 of the DDRAM in black-and-white reverse blink form (DDRAM 40H to 4FH) LB1 = 0: displays the data for line 1 of the DDRAM in standard form (no blink) (DDRAM 30H to 3FH) = 1: displays the data for line 1 of the DDRAM in black-and-white reverse blink form (DDRAM 30H to 3FH) Double Height Mode RE 1 RS 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 DH4 DB2 DH3 DB1 DH2 DB0 DH1
Double Height mode instruction field selects double height line type. DH4 = 0: displays the data for line 4 of the DDRAM in standard form (DDRAM 60H to 6FH) = 1: displays the data for line 4 of the DDRAM in vertical double size form (DDRAM 60H to 6FH) DH3 = 0: displays the data for line 3 of the DDRAM in standard form (DDRAM 50H to 5FH) = 1: displays the data for line 3 of the DDRAM in vertical double size form (DDRAM 50H to 5FH) DH2 = 0: displays the data for line 2 of the DDRAM in standard form (DDRAM 40H to 4FH) = 1: displays the data for line 2 of the DDRAM in vertical double size form (DDRAM 40H to 4FH) DH1 = 0: displays the data for line 1 of the DDRAM in standard form (DDRAM 30H to 3FH) = 1: displays the data for line 1 of the DDRAM in vertical double size form (DDRAM 30H to 3FH)
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
(1) Initial Status
(2) DD4, DD3, DD2, DD1= 1010
(3) 1-line Shift
30H -------------------- 3FH 40H -------------------- 4FH 50H -------------------- 5FH 60H -------------------- 6FH 70H -------------------- 7FH
30H -------------------- 3 FH
30H -------------------- 3FH
40H --------------- 4FH
40H --------------- 4FH
50H -------------------- 5FH
50H -------------------- 5FH
60H --------------- 6FH
60H --------------- 6FH
70H -------------------- 7FH
70H -------------------- 7FH
(4) 2-line Shift
30H -------------------- 3FH
(5) 3-line Shift
30H -------------------- 3 FH
40H --------------- 4FH
40H --------------- 4FH
DDRAM Area
50H -------------------- 5FH
50H -------------------- 5 FH
Display Area
60H --------------- 6FH
60H --------------- 6FH
XXH : DDRAM Address
70H -------------------- 7FH
70H -------------------- 7 FH
Figure 12. Line Double Height Mode Display
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
Display Control RE 0/1 RS 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 C DB2 B DB1 RE DB0 D
Display Control instruction field controls cursor / blink / display ON / OFF. C: Cursor ON / OFF control bit When C = "High", cursor is turned ON When C = "Low", cursor is disappeared in current display (default). B: Cursor blink ON / OFF control bit When C = "High" and B = "High", S6A0094 make LCD alternate between inverting display character and normal display character at the cursor position with about a half second. On the contrary, if C = "Low", only a normal character is displayed regardless of "B" flag. When B = "Low", blink is OFF (default). RE: Extended register access is specified by setting RE When RE = "High", extended register ON When RE = "Low", extended register OFF D: Display ON / OFF control bit When D = "High", entire display is turned ON. When D = "Low", display is turned OFF, but display data are remained in DDRAM (default). Table 11. Cursor Attributes C, B 1, 0 Display state
1, 1 (Blinking mode)
0, 0 0, 1
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
Power Save RE 0/1 RS 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 DB2 DB1 OS DB0 PS "-" : Don't care Power Save instruction field is used to control the oscillator and to set or to reset the power save mode. OS: oscillator ON / OFF control bit When OS = "High", internal oscillator is turned ON When OS = "Low", internal oscillator is turned OFF (default) PS: power save ON / OFF control bit When PS = "High", power save mode is turned ON When PS = "Low", power save mode is turned OFF (default) Power Control (1) RE 0 RS 0 DB7 0 DB6 1 DB5 0 DB4 1 DB3 HPM DB2 VR DB1 VF DB0 VC
Power Control instruction field sets high power mode and voltage regulator / converter / follower ON / OFF. HPM: high power mode control bit When HPM = "High", high power mode is turned ON When HPM = "Low", high power mode is turned OFF (default) VR: voltage regulator circuit control bit When VR = "High", voltage regulator is turned ON When VR = "Low", voltage regulator is turned OFF (default) VF: voltage follower circuit control bit When VF = "High", voltage follower is turned ON When VF = "Low", voltage follower is turned OFF (default) VC: voltage converter circuit control bit When VC = "High", voltage converter is turned ON When VC = "Low", voltage converter is turned OFF (default)
NOTE: The oscillation circuit must be turned on for the voltage converter circuit to be active.
Power Control (2) RE 1 RS 0 DB7 0 DB6 1 DB5 0 DB4 1 DB3 IRS DB2 BS DB1 IR1 DB0 IR0
IRS: initial resistors select When IRS = "High", internal resistors are used for regulator When IRS = "Low", external resistors are used for regulator (default) BS: bias select When BS = "High", it's 1/4 bias When BS = "Low", it's 1/5 bias (default) IR1, IR0: internal resistor ratio select When IR1,IR0 = 00, (1 + Rb/Ra) When IR1,IR0 = 01, (1 + Rb/Ra) When IR1,IR0 = 10, (1 + Rb/Ra) When IR1,IR0 = 11, (1 + Rb/Ra) = = = = 2.81, 3.27, 3.50, 3.00, V0 V0 V0 V0 = = = = 5.60V 6.54V 7.00V 6.00V
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
System Set (1) RE 0 RS 0 DB7 0 DB6 1 DB5 1 DB4 0 DB3 R1 DB2 R0 DB1 CS DB0 CG
R1, R0: selects an option ROM When R1, R0 = 00, standard ROM (160 characters) + option ROM1 (96 characters) When R1, R0 = 01, standard ROM (160 characters) + option ROM2 (96 characters) When R1, R0 = 10, standard ROM (160 characters) + option ROM3 (96 characters) When R1, R0 = 11, standard ROM (160 characters) + option ROM4 (96 characters) CS: data shift direction of common CS sets the shift direction of common display data When CS = "High", COM right shift When CS = "Low", COM left shift (default) (refer to table 9 and figure 13) CG: CGRAM enable bit When CG = "High", CGRAM can be used and you can use this RAM for eight special character area. (00h - 05h=CGRAM font display) When CG = "Low", CGRAM is disabled. CGROM (00h - 05h) can be used and the additional current consumption is saved by using this mode (default) (00h - 05h=CGROM font display) System Set (2) RE 1 RS 0 DB7 0 DB6 1 DB5 1 DB4 0 DB3 DB2 DB1 SS DB0 "-" : Don't care SS: the normal / reverse character display of SEG is specified by setting SS. When SS = "LOW", normal display of SEG When SS = `HIGH", reverse display of SEG
ROM Font
(SS, CS) = (0, 0)
(SS, CS) = (1, 0)
(SS, CS) = (0, 1)
(SS, CS) = (1, 1)
Figure 13. Example of Display according to SS and CS-bit
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
DDRAM Address Set RE 0 RS 0 DB7 1 DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Above RAM Address Set instruction field sets DDRAM and electronic volume register in the address counter. Before writing / reading data into / from the DDRAM, set the address by DDRAM Address set instruction. Next, when data are written / read in succession, the address is automatically increased by 1. After accessing 7Fh, the address of AC is 00h. The read data from the unused address are unknown. The address ranges are 00h - 7Fh. Table 12. RAM Address Mapping (RE = 0) Address 00h 10h 20h 30h 40h 50h 60h 70h
EV: Electric volume RAM TEST: Testing register, don' use it.
0
1
2
3
4
5
6
7
8 EV
9 Test
A
B
C
D
E
F
Unused
Unused
Unused Unused DDRAM line-1 DDRAM line-2 DDRAM line-3 DDRAM line-4 DDRAM line-5
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
CGRAM Address Set RE 1 RS 0 DB7 1 DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Above RAM Address set instruction field sets CGRAM, segment icon RAM in the address counter. Before writing / reading data into / from the CGRAM / ICONRAM, set the address by CGRAM Address Set instruction. Next, when data are written/read in succession, the address is automatically increased by 1. After accessing 7Fh, the address of AC is 00h. The read data from the unused address are unknown. The address ranges are 00h - 7Fh. Table 13. RAM Address Mapping (RE = 1) Address 00h 10h 20h 30h 40h 50h 60h 70h 0 1 2 3 4 5 6 7 8 9 A B C D E F
CGRAM (00H) CGRAM (02H) CGRAM (04H) Unused Unused Unused ICONRAM (S1 - S80) ICONRAM (S81 - S160)
CGRAM (01H) CGRAM (03H) CGRAM (05H)
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
Write Data RE 0/1 RS 1 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
This instruction field make S6A0094 write binary 8-bit data to DDRAM / CGRAM / ICONRAM or register. The RAM address to be written into is determined by previous DD/CGRAM Address Set instruction. After writing operation, the address counter (AC) automatically increased by 1. Read Data RE 0/1 RS 1 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
DDRAM / CGRAM / ICONRAM data read instruction. Each RAM is selected by address set instruction. And then you can read the RAM data. You can get correct RAM data from second read transaction. The first read data after setting RAM address is dummy data, so the correct RAM data come from the second read transaction. After reading operation, the address counter (AC) is increased by 1 automatically. NOP RE 0/1 RS 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
No operation command It is recommended to add this command at each breakpoint of the program. Test Mode RE 0/1 RS 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 DB2 DB1 DB0 "-" : Don't care
An IC test mode set command. Don't use it any case.
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
INITIALIZING & POWER SAVE MODE SETUP
HARDWARE RESET
When RESETB pin = "Low", S6A0094 can be initialized as the following state. (1) Control Display ON / OFF Instruction C = 0: cursor OFF B = 0: blink OFF RE = 0: extension register OFF D = 0: display OFF (2) Power Save Set Instruction OS = 0: oscillator OFF PS = 0: power save OFF (3) Power Control Set Instruction HPM = 0: high power mode OFF VR = 0: voltage regulator OFF VF = 0: voltage follower OFF VC = 0: voltage converter OFF IRS = 1: for built-in resistor BS = 0: 1/5 bias IR1, 0 = 00: Rb / Ra = 2.81 (4) System Set Instruction R1, R0 = 00: main ROM + option ROM CS = 0: COM left shift SS = 0 : normal display character CG = 0: CGRAM is not used (5) Return Home Address counter = 30h (6) Electronic Contrast Control Register: address 10h = data (0, 0, 0, 0, 0) (7) In Case of 4-bit Interface Mode Selection S6A0094 considers the first 4-bit data from MPU as the high order bits.
NOTE: If initialization is not done by the RESETB pin at application, unknown condition might result. Then you can initialize by instruction.
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
VDD RESETB
tRESETB
tRW
RESETB pulse width RESETB start time
tRW tRESETB Figure 14. RESET Timing
10s 50ns
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
INITIALIZING AND POWER SAVE SETUP
Initializing by Instruction VDD-VSS Power ON Keep RESETB Pin = "L" When the power is stable, release the reset state (RESETB = "H"). Waiting for 10us or more Command Input 1. Function Set (N, S, CG) 2. Electronic Volume Register Setup (08h) 3. Power Save (PS: Power Save OFF, OS: OSC ON) 4. Power Control (VR, VF, VC are all ON) Waiting for 500us or more Command Input 5. RAM Address set Command Input 6. Data Writing (RAM Clear) (DDRAM = 20h, CGRAM = 00h)
NOTE: At command 5 and 6, the internal RAM should be cleared. To clear DDRAM, RE bit should be set 0, set address at 30h (first DDRAM) and then write 20h (space character code) 80 times To clear CGRAM (RE=1), RE bit should be set 1, Set address at 00h (first CGRAM) and then write 00h (null data) 48 times To clear ICONRAM (RE=1), RE bit should be set 1, set ICONRAM address at 60h (first ICONRAM) and then write 00h (null data)32 times
Command Input 7. Display Control (D: ON)
End of Initialization
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
Sleep Mode Set or Release by Instruction a) Sleep Mode Set End of Initialization
Normal Operation status (Power save is OFF and oscillator is ON.)
Command Input 1. Display Control (D: OFF) 2. Power Save (PS: Power Save ON, OS: OSC OFF) 3. Power Control (VR, VF, VC are all OFF)
Enter the Sleep Mode
b) Sleep Mode Release Sleep Mode
Command input 1. Power Save (PS: Power Save OFF, OS: OSC ON) 2. Power Control (VR, VF, VC are all ON)
Waiting for 500us or more
Command Input 3. Display Control (D: ON)
Return to Normal Operation
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
Recommendation of Power ON / OFF Sequence a) Power ON Sequence Power ON
Voltage Converter ON [VR, VF, VC = 0, 0, 1] Waiting for 1ms Voltage Regulator ON [VR, VF, VC = 1, 0, 1] Waiting for 1ms Voltage Follower ON [VR, VF, VC = 1, 1, 1]
Operation Command Input
b) Power OFF Sequence Operation Command Input
Display OFF
Voltage Regulator OFF [VR, VF, VC = 0, 1, 1] Waiting for 50ms Voltage Follower OFF [VR, VF, VC = 0, 0, 1] Waiting for 1ms Voltage Converter OFF [VR, VF, VC = 0, 0, 0] Waiting for 1ms Operation Command Input
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
LCD DRIVING POWER SUPPLY CIRCUIT
The Power Supply circuit produces LCD panel driving voltage at low power consumption. The LCD driving Power Supply circuit consists of voltage converter, voltage regulator, and voltage follower. It is controlled by power control instruction. Table 14 shows how the LCD Driving Power Supply circuit works by power control instruction sets. Table 14. Power Supply Control Mode Set VR VF VC Voltage regulator Enable Voltage follower Enable Voltage converter Enable VOUT pin Internal voltage output External voltage input Open Open VR pin Used for voltage adjustment Used for voltage adjustment Open Open V0, V1, V2, V3, V4 pin Internal voltage output
111
Internal voltage output
110
Enable
Enable
Disable
010 000
Disable Disable
Enable Disable
Disable Disable
V1V4: Internal voltage output V0: External voltage input V0V4: External voltage input
NOTE: SEC recommendation is to use only the case listed above table.
VOLTAGE CONVERTER
The Voltage Converter circuit generates positive 4 times voltage of 2.0V that is generated internally. VOUT is generated from the Voltage Converter. And this conversion voltage is used in the built-in voltage regulator circuit. This application circuit is same as 3 times DC/DC converter.
VOUT
VDD
S6A0094 VDD
+
+ -
CAP1+ CAP1CAP2+ CAP2VOUT
4 x 2.0V = 8.0V
+
2.0V (Internal) VSS
-
Figure 15. DC/DC Converter Output and Circuit
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
VOLTAGE REGULATOR
The Voltage Regulator circuit is used to obtain an appropriate LCD panel driving voltage. This voltage is obtained by adjusting resistors Ra and Rb as shown in equation (1), and by setting electronic contrast control data bits, see equation (2). The potential of V0 Pin can be adjusted within VOUT - VREF. VREF is the internal constant voltage source of the chip and this value is 2.0V in the condition VDD 2.2V n Voltage regulation by adjusting resistors Ra, Rb
Rb V0 = ( 1 + Ra The internal VREF of voltage regulator has the temperature compensation function, and the temperature coefficient is approximately 0% ) x VREF --- (1)
Rb VOUT VR
_ +
V0
Ra VREF
Inside Chip
VSS GND
Figure 16. Voltage Regulator Circuit
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
ELECTRONIC CONTRAST CONTROL (32 STEPS)
Electronic Contrast Control data bits is 10h = (d4, d3, d2, d1, d0). Voltage regulation is adjusted as 32-contrast step according to the value of Electronic Contrast Control data bits. LCD drive voltage V0 has one of 32 voltage values if 5-bit data is set to the Electronic Contrast Control register (RE = 0 address 08h). When using the Electronic Contrast Control function, you need to turn the voltage regulators on using power control instruction.
Rb V0 = ( 1 + Ra VEV = VREF - n (n = 0, 1, 2, ... 30, 31) = VREF / 150 Table 15. Electronic Contrast Control Register No. 1 2 3 4 . . . 31 32 d7 . . . d6 . . . d5 . . . d4 0 0 0 0 . . . 1 1 d3 0 0 0 0 . . . 1 1 d2 0 0 0 0 . . . 1 1 d1 0 0 1 1 . . . 1 1 d0 0 1 0 1 . . . 0 1 n 0 (default) 1 2 3 . . . 30 31 V0 Maximum . . . . . . . Minimum Contrast High . . . . . . . Low ) x VEV --- (2)
NOTE: 1. "-": Don't care
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
Rb VOUT
VR
_ +
V0
Ra VREF + VEV
-
Inside Chip
VSS GND
Figure 17. Electronic Contrast Control Circuit The voltage rage of the V5 output can be adjusted by changing the built-in resister ratio (1 + Rb / Ra) by command. Reference values are shown in table 16. Table 16. V0 Voltage Regulating Built-in Resister Ratio Set Values (Reference Values) Command IR1 0 0 1 1 IR0 0 1 0 1 (1+Rb / Ra) 2.81 3.27 3.50 3.00 V0 5.60V 6.54V 7.00V 6.00V
43
S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
VOLTAGE GENERATOR CIRCUIT
VDD VDD CAP1+ CAP1CAP2+ CAP2VOUT
C1
+
C1 C1
VR
Rb Ra
GND C2 C2 C2 C2 C2 -+
V0 V1 V2 V3 V4 VSS
GND
C1: 1 ~ 4.7uF C2: 0.1uF
Figure 18. When Built-in Power Supply is used (VR, VF, VC = 1, 1, 1)
VDD VDD CAP1+ CAP1CAP2+ CAP2VOUT
VDD VDD CAP1+ CAP1CAP2+ CAP2VOUT
VDD VDD CAP1+ CAP1CAP2+ CAP2VOUT
External Power Supply
GND
VR
VR
VR
Rb Ra
GND C2 C2 C2 C2 C2 +
V0 V1 V2 V3 V4 VSS
External Power Supply
-
+
V0 V1 V2 V3 V4 VSS
External Power Supply
V0 V1 V2 V3 V4 VSS
GND
GND
GND
(VR, VF, VC = 1, 1, 0)
(VR, VF, VC = 0, 1, 0)
(VR, VF, VC = 0, 0, 0) All capacitor is C2. C2: 0.1 to 4.7uF
Figure 19. When External Power Supply is used
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
MPU INTERFACE
VDD VDD VCC A0 A1-A7 IORQ Decoder RS CSB VDD PS
S6A0094
E_RD RW_WR VDD DB[0:7] RESETB RESETB IF VSS MI
MPU
RD WR D0-D7 GND RES
Figure 20. Parallel Interfacing with 8080-series Microprocessors
VDD VDD VCC A0 A1-A7 VMA Decoder RS CSB VDD PS
S6A0094
RW_WR E_RD DB[0:7] RESETB RESETB IF VSS MI
MPU
R/W E D0-D7 GND RES
VDD
Figure 21. Parallel Interfacing with 6800-series Microprocessors
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
VDD
VCC
PORT4 PORT3
RS CSB
VDD VDD or VSS
S6A0094
MPU
PORT1 PORT2 GND RES RESETB SCL(DB6) SI(DB7) RESETB VSS
MI IF E_RD RW_WR PS
Figure 22. Clock Synchronized Serial Interfacing with any Microprocessors
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
APPLICATION INFORMAT ION FOR LCD PANEL
Chip Bottom & Lower View (CS bit = "0", DIRS = "0")
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG76
SEG77
SEG78
SEG79
SEG80
C C C C C C C C C C C C C C C C C C
O O O O O O O O O O O O O O O O O O
M I1 M 16 M 15 M 14 M 13 M 12 M 11 M 10 M9 M8 M7 M6 M5 M4 M3 M2 M1 MI1
................................................
BOTTOM VIEW
C C C C C C C C C C C C C C C C C C
O O O O O O O O O O O O O O O O O O
M I2 M 32 M 31 M 30 M 29 M 28 M 27 M 26 M 25 M 24 M 23 M 22 M 21 M 20 M 19 M 18 M 17 M I2
Figure 23. Chip Bottom & Lower View (CS bit = "0", DIRS = "0")
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
Chip Bottom & Upper View (CS bit = "1", DIRS = "1")
C C C C C C C C C C C C C C C C C C
O O O O O O O O O O O O O O O O O O
M I2 M 17 M 18 M 19 M 20 M 21 M 22 M 23 M 24 M 25 M 26 M 27 M 28 M 29 M 30 M 31 M32 M I2
BOTTOM VIEW
................................................
C C C C C C C C C C C C C C C C C C
O O O O O O O O O O O O O O O O O O
M I1 M1 M2 M3 M4 M5 M6 M7 M8 M9 M 10 M 11 M 12 M 13 M 14 M 15 M16 M I1
Figure 24. Chip Bottom & Upper View (CS bit = "1", DIRS = "1")
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG5
SEG4
SEG3
SEG2
SEG1
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
Chip Top & Lower View (CS bit = "0", DIRS = "1")
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG5
SEG4
SEG3
SEG2
SEG1
C C C C C C C C C C C C C C C C C C
O O O O O O O O O O O O O O O O O O
M I2 M 32 M 31 M 30 M 29 M 28 M 27 M 26 M 25 M 24 M 23 M 22 M 21 M 20 M 19 M 18 M17 MI2
................................................
TOP
VIEW
C C C C C C C C C C C C C C C C C C
O O O O O O O O O O O O O O O O O O
M I1 M 16 M 15 M 14 M 13 M 12 M 11 M 10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M I1
Figure 25. Chip Top & Lower View (CS bit = "0", DIRS = "1")
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
Chip Top & Upper View (CS bit = "1", DIRS = "0")
C C C C C C C C C C C C C C C C C C
O O O O O O O O O O O O O O O O O O
M I1 M1 M2 M3 M4 M5 M6 M7 M8 M9 M 10 M 11 M 12 M 13 M 14 M 15 M16 M I1
TOP
VIEW
................................................
CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO
M I2 M 17 M 18 M 19 M 20 M 21 M 22 M 23 M 24 M 25 M 26 M 27 M 28 M 29 M 30 M 31 M32 M I2
SEG10
SEG75
SEG76
SEG77
SEG79
SEG80
Figure 26. Chip Top & Upper View (CS bit = "0", DIRS = "1")
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
FRAME FREQUENCY
1/18 Duty (2-line Mode)
1-line selection period 12 V0 V1 ............. 17 18 1 2 ............. 17 18 1 2 . . . . . . . . . .
COM1
V4 VSS 1 Frame 1 Frame
1-line Selection Period = 16 Clocks One Frame = 16 x 18 x 44.44 us = 12.8 ms (1 Clock = 44.44 us at fOSC = 45 kHz) Frame Frequency = 1 / 12.8 ms = 78.1 Hz 1/26 Duty (3-line Mode)
1-line selection period 12 V0 V1 ............. 25 26 1 2 ............. 25 26 1 2 . . . . . . . . . .
COM1
V4 VSS 1 Frame 1 Frame
1-line Selection Period = 16 Clocks One Frame = 16 x 26 x 29.63 us = 12.33 ms (1 Clock = 29.63 us at fOSC = 45 kHz) Frame Frequency = 1 / 12.33 ms = 81.1 Hz 1/34 Duty (4-line Mode)
1-line selection period 12 V0 V1 ............. 33 34 1 2 ............. 33 34 1 2 . . . . . . . . . .
COM1
V4 VSS 1 Frame 1 Frame
1-line Selection Period = 16 Clocks One Frame = 16 x 34 x 22.2 us = 11.97 ms (1 Clock = 22.2 us at fOSC = 45 kHz) Frame Frequency = 1 / 11.97 ms = 83 Hz
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
MAXIMUM ABSOLUTE RAT INGS
Table 17. Maximum Absolute Ratings Characteristic Power supply voltage (1) Power supply voltage (2) Power supply voltage (3) Input voltage Operating temperature Storage temperature Symbol VDD VOUT, V0 V1, V2, V3, V4 VIN TOPR TSTG Value -0.3 to + 7.0 -0.3 to + 9.0 -0.3 to V0 -0.3 to VDD+0.3 -40 to +85 -55 to +125 Unit V V V V
o o
C C
NOTE1: All the voltage levels are based on VSS = 0V. NOTE2: Voltage greater than above may damage the circuit Voltage level : VOUT V0 VDD VSS Voltage level : V0 V1 V2 V3 V4 VSS
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
Table 18. DC Characteristics Item Operating voltage Symbol VDD IDD1 Supply current (VDD = 3V, Ta = 25 C)
o
Condition Display operation VLCD=6V without load No access from MPU Access operation from MPU (Fcyc = 200kHZ) Sleep operation without load oscillator OFF, power save ON IOH = -1mA, VDD =2.4V IOL = 1mA, VDD =2.4V VIN = 0V to VDD VIN = 0V to VDD Io = 50uA Io = 50uA VDD = 3V, Ta = 25 C (4-line mode) RL = Ta = 25 C, C = 1uF Ta = 25 C VLCD = V0 - Vss
o o o
(VDD = 2.2V to 3.6V, Ta = -40 to +85 C) Min. Typ. Max. Unit 2.2 80 3.6 110 uA V
o
IDD2 IDDS1
0.7VDD Vss VDD0.4
-
500 5 VDD 0.3VDD
Input voltage
VIH VIL VOH VOL
V
Output voltage
V 0.4
Input leakage current Output leakage current RON resistance Frame frequency (Internal OSC) Voltage converter Conversion efficiency Output voltage
IIZ IOZ RCOM RSEG fFR VEF VOUT VREF VLCD
-1 -3 70
-
1 3
uA uA k Hz
85
5 10 100
95 7.5 1.94 3.0
99 8.0 2.0 -
8.5 2.06 7.0
% V
Voltage regulator reference voltage LCD driving voltage
V
53
S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
AC CHARACTERISTICS
Parallel Write Interface (68 Mode)
(VDD = 2.2V to 3.6V, Ta = -40 to +85 C) Characteristic E_RD cycle time Pulse rise / fall time E_RD pulse width high E_RD pulse width low RS and CSB setup time RS and CSB hold time DB setup time DB hold time Symbol tC tR,tF tWH tWL tSU1 tH1 tSU2 tH2 Min. 650 450 150 60 30 100 50 Typ. Max. 25 ns Unit
o
RS,CSB
tS U 1 tH1
RW_WR
tW
H
tW tF
L
E_RD
tR tSU2 t
H2
DB0~DB7
Valid
Data tC
Figure 27. Write Timing Diagram (68-series)
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
Parallel Read Interface (68 Mode)
(VDD = 2.2V to 3.6V, Ta = -40 to +85 C) Characteristic E_RD cycle time Pulse rise / fall time E_RD pulse width high E_RD pulse width low RS and CSB setup time RS and CSB hold time DB output delay time DB output hold time Symbol tC tR,tF tWH tWL tSU tH tD tDH Min. 650 450 150 60 30 100 50 Typ. Max. 25 ns Unit
o
R S ,CSB
t SU tH
RW_WR
tW H tF tW L
E_RD
tR tD t DH
DB0~DB7
Valid
Data tC
Figure 28. Read Timing Diagram (68-series)
55
S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
Parallel Write Interface (80 Mode)
(VDD = 2.2V to 3.6V, Ta = -40 to +85 C) Characteristic RW_WR cycle time Pulse rise / fall time RW_WR pulse width high RW_WR pulse width low RS and CSB setup time RS and CSB hold time DB setup time DB hold time Symbol tC tR,tF tWH tWL tSU1 tH1 tSU2 tH2 Min. 650 150 450 60 30 100 50 Typ. Max. 25 ns Unit
o
R S ,CSB
tSU1 t H1
E_RD
tW L tR tW H
RW_WR
tF t SU2 t H2
DB0~DB7
Valid
Data tC
Figure 29. Write Timing Diagram (80-series)
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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
S6A0094
Parallel Read Interface (80 Mode)
(VDD = 2.2V to 3.6V, Ta = -40 to +85 C) Characteristic E_RD cycle time Pulse rise / fall time E_RD pulse width high E_RD pulse width low RS and CSB setup time RS and CSB hold time DB output delay time DB output hold time Symbol tC tR,tF tWH tWL tSU tH tD tDH Min. 650 150 450 60 30 100 50 Typ. Max. 25 ns Unit
o
R S ,CSB
t SU tH
RW_WR
tW L tR tW H
E_RD
tF tD t DH
DB0~DB7
Valid
Data tC
Figure 30. Read Timing Diagram (80-series)
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S6A0094
80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD
Clock Synchronized Serial Mode
(VDD = 2.2V to 3.6V, Ta = -40 to +85 C) Characteristic SCL clock cycle time Pulse rise / fall time SCL clock width (high, low) CSB setup time CSB hold time RS data setup time RS data hold time SI data setup time SI data hold time Symbol tC tR,tF tW tSU1 tH1 tSU2 tH2 tSU3 tH3 Min. 1000 300 150 700 50 300 50 50 Typ. Max. 25 ns Unit
o
tSU1
tC
tH1
CSB
tR tW tF tW
SCL
tSU2
tH2
RS
tSU3 tH3
SI
Figure 31. Clock Synchronized Serial Interface Mode Timing Diagram
58

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